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INTERGRATED CIRCUITS
DATA SHEET
SAA7120H; SAA7121H Digital video encoder
Product specification Supersedes data of 1997 Jan 06 2002 Oct 11
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 8.1 8.2 9 9.1 10 11 11.1 11.2 11.3 11.4 11.5 12 13 14 15 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Data manager Encoder Output interface/DACs Synchronization I2C-bus interface Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter CHARACTERISTICS Explanation of RTCI data bits Teletext timing APPLICATION INFORMATION Analog output voltages PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
SAA7120H; SAA7121H
2002 Oct 11
2
Philips Semiconductors
Product specification
Digital video encoder
1 FEATURES
SAA7120H; SAA7121H
* Monolithic CMOS 3.3 V device * Digital PAL/NTSC encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data on 8-bit wide input port; input data format CB-Y-CR (CCIR 656) * Three Digital-to-Analog Converters (DACs) for Y, C and CVBS two times oversampled with 10-bit resolution * Real-time control of subcarrier * Cross-colour reduction filter * Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter * Line 23 Wide Screen Signalling (WSS) encoding * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * 2 x 2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus * Down mode of DACs * Controlled rise/fall times of synchronization and blanking output signals * MacrovisionTM(1) Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to SAA7120H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information * QFP44 package. 2 GENERAL DESCRIPTION
The SAA7120H; SAA7121H encodes digital YUV video data to an NTSC or PAL CVBS or S-video signal. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip DACs.
(1) MacrovisionTM is a trademark of the Macrovision Corporation.
3
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME SAA7120H SAA7121H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
4 QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL LElf(i) LElf(d) Tamb 5 analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C and CVBS without load (peak-to-peak value) load resistance low frequency integral linearity error low frequency differential linearity error ambient temperature PARAMETER
SAA7120H; SAA7121H
MIN. 3.1 3.0 - - - 75 - - 0
TYP. 3.3 3.3 55 32 1.35 - - - -
MAX. 3.5 3.6 62 45 - 300 3 1 70
UNIT V V mA mA V LSB LSB C
TTL compatible
BLOCK DIAGRAM
handbook, full pagewidth
VDDA1, RCV1 TTXRQ XTALO XCLK LLC VDDA2, VDDA3 VDDA4 RCV2 XTALI
RESET SDA SCL SA 40 42 41 21
7
8
43 37 34 35 4
25, 28, 31
36
I2C-BUS INTERFACE I2C-bus control
SAA7120H SAA7121H
SYNC CLOCK I2C-bus control
clock and timing Y Y ENCODER C
MP7 to MP0
9 to 16 DATA MANAGER
30 OUTPUT INTERFACE D A 27 24
CVBS Y C
CB-CR
I2C-bus control TTX 44
I2C-bus control
I2C-bus control
32, 33
VSSA1 VSSA2
5, 18, 38 VSSD1, VSSD2, VSSD3
6, 17, 39 VDDD1, VDDD2, VDDD3
1, 20, 22, 23, 26, 29 RES
19 RTCI
2 SP
3
MBH787
AP
Fig.1 Block diagram.
2002 Oct 11
4
Philips Semiconductors
Product specification
Digital video encoder
6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TYPE - I I I supply supply I/O I/O I I I I I I I I supply supply I digital supply voltage 2 digital ground 2 reserved
SAA7120H; SAA7121H
SYMBOL RES SP AP LLC VSSD1 VDDD1 RCV1 RCV2 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VDDD2 VSSD2 RTCI
DESCRIPTION test pin; connected to digital ground for normal operation test pin; connected to digital ground for normal operation line-locked clock; this is the 27 MHz master clock for the encoder digital ground 1 digital supply voltage 1 raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MPEG ports; inputs for "CCIR 656" style multiplexed CB-Y-CR data
real-time control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality reserved the I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH reserved reserved analog output of the chrominance signal analog supply voltage 1 for the C DAC reserved analog output of VBS signal analog supply voltage 2 for the Y DAC reserved analog output of the CVBS signal analog supply voltage 3 for the CVBS DAC analog ground 1 for the DACs analog ground 2 for the oscillator and reference voltage crystal oscillator output crystal oscillator input; if the oscillator is not used, this pin should be connected to ground analog supply voltage 4 for the oscillator and reference voltage 5
RES SA RES RES C VDDA1 RES Y VDDA2 RES CVBS VDDA3 VSSA1 VSSA2 XTALO XTALI VDDA4 2002 Oct 11
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
- I - - O supply - O supply - O supply supply supply O I supply
Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
SYMBOL XCLK VSSD3 VDDD3 RESET SCL SDA TTXRQ TTX
PIN 37 38 39 40 41 42 43 44
TYPE O supply supply I I I/O O I digital ground 3 digital supply voltage 3
DESCRIPTION clock output of the crystal oscillator
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. I2C-bus serial clock input I2C-bus serial data input/output teletext request output, indicating when bit stream is valid teletext bit stream input
39 VDDD3
43 TTXRQ
36 VDDA4
40 RESET
38 VSSD3
35 XTALI
37 XCLK
handbook, full pagewidth
34 XTALO
42 SDA
41 SCL
44 TTX
RES 1 SP 2 AP 3 LLC 4 VSSD1 5 VDDD1 6 RCV1 7 RCV2 8 MP7 9 MP6 10 MP5 11
33 VSSA2 32 VSSA1 31 VDDA3 30 CVBS 29 RES
SAA7120H SAA7121H
28 VDDA2 27 Y 26 RES 25 VDDA1 24 C 23 RES
MP4 12
MP3 13
MP2 14
MP1 15
MP0 16
VDDD2 17
VSSD2 18
RTCI 19
RES 20
SA 21
RES 22
MBH790
Fig.2 Pin configuration.
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
7 FUNCTIONAL DESCRIPTION 7.1
SAA7120H; SAA7121H
Data manager
The digital video encoder encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-video signals. NTSC-M, PAL-B/G and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "CCIR 624". For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. The total filter transfer characteristics are illustrated in Figs 3 to 6. The DACs for Y, C and CVBS are realized with full 10-bit resolution. The 8-bit multiplexed CB-Y-CR formats are "CCIR 656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. It is also possible to connect a Philips digital video decoder (SAA7111 or SAA7151B) to this encoder. By connecting pin RTCI to pin RTCO of a decoder, information about the actual subcarrier, PAL-ID and (with SAA7111 and newer types) definite subcarrier phase can be inserted. The digital video encoder synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using 50 Hz field rate. The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. A number of possibilities are provided for setting different video parameters, such as: * Black and blanking level control * Colour subcarrier frequency * Variable burst amplitude, etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H, registers 6BH and 6EH to 00H and bit TTX60 to 0. No other control registers are influenced by a reset. 2002 Oct 11 7
Real-time arbitration on the data stream to be encoded is performed in the data manager. A pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source. The colour bar function is under software control only. 7.2 7.2.1 Encoder VIDEO PATH
The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process such as additional insertion of AGC super-white pulses (programmable in height) are supported by the SAA7120H only. In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 5 and 6. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 3 and 4. The amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in a 10-bit resolution is provided on the subcarrier. The numeric ratio between Y and C outputs is in accordance with the respective standards.
Philips Semiconductors
Product specification
Digital video encoder
7.2.2 TELETEXT INSERTION AND ENCODING
SAA7120H; SAA7121H
Outputs of the DACs can be set together in two groups, via software control, to a minimum output voltage for either purpose. 7.4 Synchronization
Pin TTX receives a WST or NABTS teletext bitstream sampled at the LLC clock. At each rising edge of output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at the input pin. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.10. 7.2.3 CLOSED CAPTION ENCODER
The synchronization of the SAA7120H; SAA7121H is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and the on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it also can be used to set the horizontal phase. If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be applied to pin RCV2. Timing and trigger behaviour can also be influenced for the signal at pin RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of the IC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (with the incorrect phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Alternatively, the device can be triggered by auxiliary codes in a "CCIR 656" data stream at the MP port. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the device can output: * A Vertical Sync (VS) signal with 3 or 2.5 lines duration * An odd/even signal which is LOW in odd fields * A Field Sequence (FSEQ) signal which is HIGH in the first of 4 or 8 fields respectively. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. The length of a field and the start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line.
Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.2.4 ANTI-TAPING (SAA7120H ONLY)
For more information contact your nearest Philips Semiconductors sales office. 7.3 Output interface/DACs
In the output interface, encoded Y and C signals are converted from digital-to-analog in a 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. 2002 Oct 11 8
Philips Semiconductors
Product specification
Digital video encoder
7.5 I2C-bus interface
SAA7120H; SAA7121H
Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. Table 1
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. The I2C-bus slave address is defined as 88H with pin 21 (SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH. 7.6 Input levels and formats
"CCIR 601" signal component levels
SIGNALS
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black 235 210 170 145 106 81 41 16 CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128
The SAA7120H; SAA7121H expects digital Y, CB and CR data with levels (digital codes) in accordance with "CCIR 601". For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Table 2 8-bit multiplexed format (similar to "CCIR 601")
BITS TIME 0 Sample Luminance pixel number Colour pixel number CB0 0 0 1 Y0 2 CR0 1 3 Y1 4 CB2 2 2 5 Y2 6 CR2 3 7 Y3
2002 Oct 11
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Digital video encoder
Table 3
Slave receiver (slave address 88H or 8CH) DATA BYTE(1) SUBADDR D7 D6 0 WSS6 0 DECFIS 0 CGO06 CGO16 CGE06 CGE16 CGEN0 0 0 CHPS6 GAINU6 GAINV6 DECOE DECPH CCRS0 0 DOWN BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 0 WSS5 WSS13 BS5 BE5 CGO05 CGO15 CGE05 CGE15 0 0 0 CHPS5 GAINU5 GAINV5 BLCKL5 BLNNL5 BLNVB5 0 INPI BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 D5 0 WSS4 WSS12 BS4 BE4 CGO04 CGO14 CGE04 CGE14 0 0 SYMP CHPS4 GAINU4 GAINV4 BLCKL4 BLNNL4 BLNVB4 0 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 D4 0 WSS3 WSS11 BS3 BE3 CGO03 CGO13 CGE03 CGE13 0 0 0 CHPS3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3 0 0 BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 D3 0 WSS2 WSS10 BS2 BE2 CGO02 CGO12 CGE02 CGE12 0 0 0 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 D2 0 WSS1 WSS9 BS1 BE1 CGO01 CGO11 CGE01 CGE11 0 0 Y2C CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 D1 0 WSS0 WSS8 BS0 BE0 CGO00 CGO10 CGE00 CGE10 0 0 UV2C CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 D0 00H to 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH to 39H 3AH 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 0 WSS7 WSSON DECCOL 0 CGO07 CGO17 CGE07 CGE17 CGEN1 0 CBENB CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1 0 0 RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17
REGISTER FUNCTION Null Wide screen signal Wide screen signal Real-time control, burst start Burst end Copy guard odd 0 Copy guard odd 1 Copy guard even 0 Copy guard even 1 Copy guard enable Null Input port control Chrominance phase Gain U Gain V Gain U MSB, real-time control, black level Gain V MSB, real-time control, blanking level CCR, blanking level VBI Null Standard control RTC enable, burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1
SAA7120H; SAA7121H
BLNVB0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10
Product specification
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Digital video encoder SAA7120H; SAA7121H
Product specification
Philips Semiconductors
Product specification
Digital video encoder
7.8 I2C-bus format I2C-bus address; see Table 5 ACK SUBADDRESS ACK DATA 0
SAA7120H; SAA7121H
Table 4 S
SLAVE ADDRESS
ACK --------
DATA n
ACK P
Table 5
Explanation of Table 4 PART DESCRIPTION START condition 1000 100X or 1000 110X; note 1 acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S SLAVE ADDRESS ACK SUBADDRESS; note 2 DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. 7.9 Slave receiver Subaddresses 26H and 27H LOGIC LEVEL - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 1 Table 7 wide screen signalling output is disabled; default after reset wide screen signalling output is enabled DESCRIPTION
Table 6
DATA BYTE WSS
Subaddresses 28H and 29H LOGIC LEVEL - - 0 1 0 1 DESCRIPTION starting point of burst in clock cycles ending point of burst in clock cycles disable colour detection bit of RTCI input enable colour detection bit of RTCI input field sequence as FISE in subaddress 61 field sequence as FISE bit in RTCI input bit RTCE must be set to logic 1 (see Fig.9) bit RTCE must be set to logic 1 (see Fig.9) REMARKS PAL: BS = 33 (21H); default after reset NTSC: BS = 25 (19H) PAL: BE = 29 (1DH); default after reset NTSC: BE = 29 (1DH)
DATA BYTE BS BE DECCOL DECFIS
2002 Oct 11
12
Philips Semiconductors
Product specification
Digital video encoder
Table 8 Subaddresses 2AH to 2DH DATA BYTE CGO0 CGO1 CGE0 CGE1 Table 9 Subaddress 2EH DATA BYTE DESCRIPTION first byte of copy guard data, odd field
SAA7120H; SAA7121H
REMARKS
LSBs of the respective bytes are encoded immediately after run-in and framing code, second byte of copy guard data, odd field the MSBs of the respective bytes have to first byte of copy guard data, even field carry the parity bit, in accordance with the second byte of copy guard data, even field definition of line 20 encoding format
DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 copy guard encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 10 Subaddress 3AH DATA BYTE UV2C Y2C SYMP LOGIC LEVEL 0 1 0 1 0 1 CBENB 0 1 Table 11 Subaddress 5AH DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees VALUE 00H 2AH 88H AAH RESULT PAL-B/G and data from input ports PAL-B/G and data from look-up table NTSC-M and data from input ports NTSC-M and data from look-up table CB, CR data are twos complement CB, CR data are straight binary; default after reset Y data is twos complement Y data is straight binary; default after reset horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset horizontal and vertical trigger is decoded out of "CCIR 656" compatible data at MP port data from input ports is encoded; default after reset colour bar with fixed colours is encoded DESCRIPTION
2002 Oct 11
13
Philips Semiconductors
Product specification
Digital video encoder
Table 12 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) Table 13 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFH) Table 14 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with "CCIR 601" CONDITIONS white-to-sync = 140 IRE; note 1 BLCKL = 0; note 1 BLCKL = 63 (3FH); note 1 white-to-sync = 143 IRE; note 2 BLCKL = 0; note 2 BLCKL = 63 (3FH); note 2 DECOE real-time control logic 0 logic 1 Notes 1. Output black level/IRE = BLCKL x 2/6.29 + 34.0. 2. Output black level/IRE = BLCKL x 2/6.18 + 31.7.
SAA7120H; SAA7121H
REMARKS GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
REMARKS GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
REMARKS recommended value: BLCKL = 42 (2AH) output black level = 34 IRE output black level = 54 IRE recommended value: BLCKL = 35 (23H) output black level = 32 IRE output black level = 52 IRE disable odd/even field control bit from RTCI enable odd/even field control bit from RTCI (see Fig.9)
2002 Oct 11
14
Philips Semiconductors
Product specification
Digital video encoder
Table 15 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE; note 1 BLNNL = 0; note 1 BLNNL = 63 (3FH); note 1 white-to-sync = 143 IRE; note 2 BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 DECPH real-time control logic 0 logic 1 Notes 1. Output black level/IRE = BLNNL x 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35H. Table 16 Subaddress 5FH DATA BYTE BLNVB CCRS DESCRIPTION
SAA7120H; SAA7121H
REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE disable subcarrier phase reset bit from RTCI enable subcarrier phase reset bit from RTCI (see Fig.9)
variable blanking level during vertical blanking interval is typically identical to value of BLNNL select cross-colour reduction filter in luminance; see Table 17
Table 17 Logic levels and function of CCRS CCRS1 0 0 1 1 CCRS0 0 1 0 1 DESCRIPTION no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5 cross-colour reduction #1 active; for overall transfer characteristic see Fig.5 cross-colour reduction #2 active; for overall transfer characteristic see Fig.5 cross-colour reduction #3 active; for overall transfer characteristic see Fig.5
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Philips Semiconductors
Product specification
Digital video encoder
Table 18 Subaddress 61H DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 1 YGS INPI DOWN 0 1 0 1 0 1 Table 19 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL 0 1 858 total pixel clocks per line NTSC encoding (non-alternating V component)
SAA7120H; SAA7121H
DESCRIPTION 864 total pixel clocks per line; default after reset
PAL encoding (alternating V component); default after reset enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset luminance gain for white - black 100 IRE; default after reset luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 19 DACs for CVBS, Y and C in normal operational mode; default after reset DACs for CVBS, Y and C forced to lowest output voltage
DESCRIPTION no real-time control of generated subcarrier frequency; default after reset real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for timing see Fig.9
Table 20 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "CCIR 601" CONDITIONS REMARKS
white-to-black = 92.5 IRE; recommended value: burst = 40 IRE; NTSC encoding BSTA = 63 (3FH) BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; recommended value: burst = 43 IRE; NTSC encoding BSTA = 67 (43H) BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal recommended value: BSTA = 47 (2FH); default after reset recommended value: BSTA = 45 (2DH)
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
Table 21 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE FSC0 to FSC3 DESCRIPTION fsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS f sc 32 FSC = round ------ x 2 ; f llc note 1 REMARKS FSC3 = most significant byte; FSC0 = least significant byte
Note 1. Examples: a) NTSC-M: fsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: fsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 22 Subaddresses 67H to 6AH DATA BYTE L21O0 L21O1 L21E0 L21E1 DESCRIPTION first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format
Table 23 Subaddress 6BH DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a `composite-blanking-not' signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 ORCV1 TRCV2 0 1 0 1 0 1 SRCV1 2002 Oct 11 - polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of "CCIR 656" input (at bit SYMP = HIGH); default after reset horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) defines signal type on pin RCV1; see Table 24 17
Philips Semiconductors
Product specification
Digital video encoder
Table 24 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 1 SRCV10 0 1 0 1 VS FS FSEQ - VS FS FSEQ - AS INPUT
SAA7120H; SAA7121H
FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) not applicable
Table 25 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H) Table 26 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH) Table 27 Subaddress 6EH DATA BYTE SBLBN PHRES FLC LOGIC LEVEL 0 1 - - DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset vertical blanking is forced in accordance with "CCIR 624" (50 Hz) or RS170A (60 Hz) selects the phase reset mode of the colour subcarrier generator; see Table 28 field length control; see Table 29
Table 28 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset reset every two lines reset every eight fields reset every four fields
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Philips Semiconductors
Product specification
Digital video encoder
Table 29 Logic levels and function of FLC DATA BYTE
SAA7120H; SAA7121H
DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6FH DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - DESCRIPTION enables individual line 21 encoding; see Table 31 disables teletext insertion; default after reset enables teletext insertion selects the actual line, where closed caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 31 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding off; default after reset enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 32 Subaddresses 70H to 72H DATA BYTE RCV2S start of output signal on pin RCV2 values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH (0FDH) RCV2E end of output signal on pin RCV2 values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H) Table 33 Subaddresses 73H and 74H DATA BYTE TTXHS TTXHD DESCRIPTION start of signal on pin TTXRQ; see Fig.10 indicates the delay in clock cycles between rising edge of TTXRQ output and valid data at pin TTX REMARKS PAL: TTXHS = 42H NTSC: TTXHS = 54H minimum value: TTXHD = 2 DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
Table 34 Subaddress 75H DATA BYTE VS_S DESCRIPTION vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00)
SAA7120H; SAA7121H
REMARKS standard value: VS_S = 3
Table 35 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION first line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems Table 36 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION first line of occurrence of signal on pin TTXRQ in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal on pin TTXRQ in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 37 Subaddresses 7AH to 7CH DATA BYTE FAL DESCRIPTION first active line: measured in lines; FAL = 0 coincides with the first field synchronization pulse first active line = (FAL + 4) for M systems first active line = (FAL + 1) for other systems LAL last active line: measured in lines; LAL = 0 coincides with the first field synchronization pulse last active line = (LAL + 3) for M-systems last active line = LAL for other systems Table 38 Subaddress 7CH DATA BYTE TTX60 LOGIC LEVEL 0 1 DESCRIPTION enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset enables world standard teletext 60 Hz (FISE = 1) PAL: TTXEVE = 16H; NTSC: TTXEVE = 10H REMARKS PAL: TTXEVS = 04H; NTSC: TTXEVS = 05H PAL: TTXOVE = 16H; NTSC: TTXOVE = 10H REMARKS PAL: TTXOVS = 05H; NTSC: TTXOVS = 06H
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Philips Semiconductors
Product specification
Digital video encoder
Table 39 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION
SAA7120H; SAA7121H
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate); this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up. 7.10 Slave transmitter
Table 40 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3 D2 FSEQ2 D1 FSEQ1 D0 O_E CCRDO CCRDE
Table 41 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E - 1 0 DESCRIPTION version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 001 binary closed caption bytes of the odd field have been encoded the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded closed caption bytes of the even field have been encoded the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded state of the internal field sequence counter, with bit O_E as LSB (repetition rate: NTSC = 4 fields, PAL = 8 fields) during even field during odd field
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Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) SCBW = 1. (2) SCBW = 0.
Fig.3 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 2.
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(4) (2) (3) (1)
6
MGD672
(1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0.
(3) CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0.
Fig.5 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.6 Luminance transfer characteristic 2.
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Philips Semiconductors
Product specification
Digital video encoder
8 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD VIL VIH ILI Ci analog supply voltage digital supply voltage analog supply current digital supply current note 1 PARAMETER CONDITIONS
SAA7120H; SAA7121H
MIN.
MAX.
UNIT
3.1 3.0 - - -0.5 2.0 - clocks data I/Os at high-impedance - - - VDDD = 3.3 V; note 1
3.5 3.6 62 45
V V mA mA
Inputs: LLC, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX LOW-level input voltage HIGH-level input voltage input leakage current input capacitance +0.8 VDDD + 0.3 1 10 8 8 V V A pF pF pF
Outputs: RCV1, RCV2 and TTXRQ VOL VOH I2C-bus: VIL VIH Ii VOL Io TLLC tr tf tSU;DAT tHD;DAT LOW-level output voltage HIGH-level output voltage SDA and SCL LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 0.7VDDD -10 - 3 +0.3VDDD VDDD + 0.3 +10 0.4 - 41 60 5 6 - - V V A V mA IOL = 2 mA IOH = -2 mA - 2.4 0.4 - V V
Clock timing: LLC cycle time duty factor tHIGH/TLLC rise time fall time note 2 note 3 note 2 note 2 34 40 - - 6 3 ns % ns ns
Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX input data set-up time input data hold time ns ns
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Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 CL th td Vo(p-p) Rint RL B LElf(i) LElf(d) Notes
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 4
30
MHz
-50 x 10-6 +50 x 10-6 0 8 - 1.5 - 20% 3.5 - 20% 7.5 4 - 70 - 80 1.5 + 20% 3.5 + 20% C pF fF pF
CRYSTAL SPECIFICATION ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical)
Data and reference signal output timing output load capacitance output hold time output delay time 40 - 25 pF ns ns
C, Y and CVBS outputs output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs -3 dB note 5 1.25 1 75 10 - - 1.50 3 300 - 3 1 V MHz LSB LSB
1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 5. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.7 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
CB(0)
Y(0)
CR(0)
Y(1)
CB(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S).
Fig.8 Functional timing.
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
8.1 Explanation of RTCI data bits
SAA7120H; SAA7121H
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7120H; SAA7121H ignores its internally generated odd/even flag and takes the odd/even bit from RTCI input. 7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the SAA7120H; SAA7121H. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input.
1. The HPLL increment is not evaluated by the SAA7120H; SAA7121H. 2. The SAA7120H; SAA7121H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.). 3. The PAL bit indicates the line with inverted (R - Y) component of colour difference signal. 4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1. 5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7120H; SAA7121H takes this bit instead of the FISE bit in subaddress 61H.
HIGH-to-LOW transition handbook, full pagewidth count start 128 RTCI
13
4 bits reserved HPLL increment (1)
0 22
3 bits reserved FSCPLL increment (2)
0 (4) (3)
LOW
(5) (6)
(7)
time slot: 0 1
14
19
64
67 69 68
72 74
not used in SAA7120H/21H
valid sample
invalid sample
8/LLC
MBH789
(8)
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment. (2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit. (3) Sequence bit: PAL: 0 = (R - Y) line normal, 1 = (R - Y) line inverted; NTSC: 0 = no change. (4) Reset bit: only from SAA7111 and SAA7112 decoder. (5) (6) (7) (8) FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd_even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
Fig.9 RTCI timing.
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
8.2 Teletext timing
SAA7120H; SAA7121H
Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (WST) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is logic 0. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion.
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and Y output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse.
handbook, full pagewidth
CVBS/Y tTTX textbit #: TTX 1 2 3 4 5 6 7 8 9 10 11 12 tTTXWin 13 14 15 16 17 18 19 20 21 22 23 24
tPD
tFD
TTXRQ
MBH788
Fig.10 Teletext timing.
2002 Oct 11
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DGND +3.3 V digital 10 H 1 nF 10 pF 27.0 MHz X1 3rd harmonic XTALI 35 XTALO 34 10 pF +3.3 V analog 0.1 F AGND 0.1 F DGND 0.1 F AGND VDDD1, VDDD2, VDDD3 6, 17, 39 use one capacitor for each VDDD VDDA4 36 DAC1 VDDA1 25 VDDA2 28 VDDA3 31 2 (1) 30 CVBS 4.7 75 2 (1) 10 75 digital inputs and outputs UCVBS 1.23 V (p-p)(2) AGND 0.1 F AGND 0.1 F AGND
9
Philips Semiconductors
Digital video encoder
APPLICATION INFORMATION
(1) Typical value. (2) For 100100 colour bar.
Fig.11 Application circuit.
handbook, full pagewidth
29
DAC2 27 Y
UY 1.00 V (p-p)(2) AGND
SAA7120H SAA7121H
DAC3
2 (1)
24
C
10 75
UC 0.89 V (p-p)(2) AGND
SAA7120H; SAA7121H
5, 18, 38 VSSD1, VSSD2, VSSD3 DGND
32, 33 VSSA1, VSSA2 AGND
MBH786
Product specification
Philips Semiconductors
Product specification
Digital video encoder
9.1 Analog output voltages
SAA7120H; SAA7121H
The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor (typical value 2 ), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 42 for a 100100 colour bar signal. Values for the external series resistors result in a 75 load. Table 42 Digital output signals conversion range CONVERSION RANGE (peak-to-peak) CVBS SYNC-TIP TO PEAK-CARRIER (digits) 1016 Y (VBS) SYNC-TIP TO WHITE (digits) 881
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
10 PACKAGE OUTLINE
SAA7120H; SAA7121H
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
2002 Oct 11
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Philips Semiconductors
Product specification
Digital video encoder
11 SOLDERING 11.1 Introduction to soldering surface mount packages
SAA7120H; SAA7121H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 11.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 11.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 11.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Oct 11
32
Philips Semiconductors
Product specification
Digital video encoder
11.5
SAA7120H; SAA7121H
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
not suitable not suitable(3)
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Oct 11
33
Philips Semiconductors
Product specification
Digital video encoder
12 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
SAA7120H; SAA7121H
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Oct 11
34
Philips Semiconductors
Product specification
Digital video encoder
15 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7120H; SAA7121H
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Oct 11
35
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/02/pp36
Date of release: 2002
Oct 11
Document order number:
9397 750 09829

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